Please refer to FIG. 1A for an active area of a conventional N-channel trench MOSFET structure of prior art (U.S. Pat. No. 6,888,196) with n+ source regions having a same surface doping concentration and a same junction depth along a trenched source-body contact and a channel region. The disclosed N-channel trench MOSFET cell is formed in an N epitaxial layer 102 supported on an N+ substrate 100. Near a top surface of a P body region 103, which is formed within the N epitaxial layer 102, an n+ source region 104 is implanted flanking trenched gates formed in trenches 105 and adjacent to sidewalls of a trenched source-body contact 106. As mentioned above, the n+ source region 104 has a same doping concentration at a same distance from a top surface of the N epitaxial layer 102, and the n+ source region 104 has a same junction depth (Ds, as illustrated in FIG. 1A) from the top surface of the N epitaxial layer 102, which is related to the formation method of the n+ source region 104.
FIG. 1B shows the fabrication method of the n+ source region 104. After formation of the P body region 103 and its diffusion step, the n+ source region 104 is formed by performing a source dopant ion implantation through a source mask (not shown). The top surface of the P body region 103 suffered the same source dopant ion implantation and the same dopant diffusion step, therefore the n+ source region 104 has a same doping concentration at a same distance from the top surface of the N epitaxial layer 102, and the n+ source region 104 has a same junction depth from the top surface of the N epitaxial layer 102.
This uniform distribution of the doping concentration and the junction depth of the n+ source region may lead to a hazardous failure during a UIS (Unclamped Inductance Switching) test, please refer to FIG. 1C for a top view of the n+ source region 104 and the trenched source-body contact 106 shown in FIG. 1A. As illustrated, Rbe is a base resistance from the trenched source-body contact 106 to a cell corner; Rbe is a base resistance from the trenched source-body contact 106 to a cell edge. Obviously, Rbc is greater than Rbe because the distance from the trenched source-body contact 106 to the cell corner is longer than that from the trenched source-body contact 106 to the cell edge, resulting in UIS failure occurring at trench corners and a poor avalanche capability for closed cells at cell corners because a parasitic NPN bipolar transistor (as illustrated in FIG. 1A) is easily turned on.
FIG. 1D is a top view of the conventional trench MOSFET of prior art. After the UIS test, failed sites always occur near an edge of the active area of the trench MOSFET, as shown in FIG. 1D, which is resulted from the turning on of the parasitic bipolar transistor, as illustrated in FIG. 1A. The trenched gates in an edge trench (as illustrated in FIG. 1D) near the edge of the active area are turned on first when bias voltage on a gate metal runner is increasing for turning on a channel region, resulting in the parasitic bipolar transistor turning on first near the edge of the active area, thus weakening the avalanche capability of the trench MOSFET.
Accordingly, it would be desirable to provide a new and improved device configuration to enhance the avalanche capability of semiconductor power devices.